PLL[ 0 ] = 0x0
PLL[ 1 ] = 0x8005
PLL[ 2 ] = 0xa700
PLL[ 3 ] = 0xc
PLL[ 4 ] = 0x70086
PLL[ 5 ] = 0x70097
PLL[ 6 ] = 0x3005a
PLL[ 7 ] = 0x30065
PLL[ 8 ] = 0xc3
PLL[ 9 ] = 0x0
PLL[ a ] = 0x66510c
PLL[ b ] = 0x58001200
PLL[ c ] = 0x400bc30
PLL[ d ] = 0x2
PLL[ e ] = 0x400a400
PLL[ f ] = 0x980098
PLL[ 10 ] = 0x800080
PLL[ 11 ] = 0x800080
PLL[ 12 ] = 0xaa3a1212
PLL[ 13 ] = 0x18000200
PLL[ 14 ] = 0x13100
PLL[ 15 ] = 0xc007c000
PLL[ 16 ] = 0x0
PLL[ 17 ] = 0x0
PLL[ 18 ] = 0xffffffef
PLL[ 19 ] = 0x8000
PLL[ 1a ] = 0x0
PLL[ 1b ] = 0x0
PLL[ 1c ] = 0x1b300003
PLL[ 1d ] = 0x0
PLL[ 1e ] = 0x0
PLL[ 1f ] = 0x3000
PLL[ 20 ] = 0x15000000
PLL[ 21 ] = 0x300f939
PLL[ 22 ] = 0x8000640a
PLL[ 23 ] = 0x0
PLL[ 24 ] = 0x1001
PLL[ 25 ] = 0x6
PLL[ 26 ] = 0x0
PLL[ 27 ] = 0x0
PLL[ 28 ] = 0x0
PLL[ 29 ] = 0x0
PLL[ 2a ] = 0xa403
PLL[ 2b ] = 0x0
PLL[ 2c ] = 0x0
PLL[ 2d ] = 0xf8c0
Clock Chip Type: 0x9
Struct size    : 0x32
Acceleartor Entry: 0x3
VGA Entry      : 0x3
VGA Table offset:0x666
Post table offset: 0x65e
XCLK           : 0x477c
MCLK           : 0x59d8
num PLL blocks : 0x3
size PLL blocks: 0xc
PCLK ref freq  : 0xa8c
PCLK ref div   : 0xc
PCLK min freq  : 0x4e20
PCLK max freq  : 0x9c40
MCLK ref freq  : 0xa8c
MCLK ref div   : 0xc
MCLK min freq  : 0x4e20
MCLK max freq  : 0x9c40
XCLK ref freq  : 0xa8c
XCLK ref div   : 0xc
XCLK min freq  : 0x4e20
XCLK max freq  : 0x9c40
