RAGE 128 Register Reference Supplement
Digital Flat Panel Interface Registers

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Digital Flat Panel Interface Registers Detailed Register Reference 
Set the parameters that affect LCD panel output and control the TMDS transmitter

FP_CRTC_H_TOTAL_DISP   MMR:0x0250 MMR_1:0x0250 IND:0x0250 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_CRTC_H_TOTAL 	8:0 	0x0 	Shadow version of the Horizontal total (pixels * 8) for flat panel display. Sum of display width, overscan right, front porch, sync width, back porch and overscan left.

(reserved) 	15:9 	  	  
	
FP_CRTC_H_DISP 	23:16 	0x0 	Shadow version of horizontal display end (pixels * 8) for flat panel display. Determines number of visible pixels, not including overscan.
	
(reserved) 	31:24 	  	  
	
 FP_CRTC_H_TOTAL_DISP: Shadow versions of the CRTC_H_TOTAL and CRTC_H_DISP registers for use during DFP operations, These contain separate values used for panel output. They are used when FP_USE_SHADOW_EN field in FP_GEN_CNTL register is set to ‘1’.

FP_CRTC_V_TOTAL_DISP   MMR:0x0254 MMR_1:0x0254 IND:0x0254 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_CRTC_V_TOTAL 	10:0 	0x0 	Shadow version of the Vertical total (in lines). Sum of display height, overscan bottom, front porch, sync width, back porch and overscan top.

(reserved) 	15:11 	  	  
	
FP_CRTC_V_DISP 	26:16 	0x0 	Shadow version of the Vertical Display End. Determines number of visible lines, not including overscan.

(reserved) 	31:27 	  	  
	
 FP_CRTC_V_TOTAL_DISP: Shadow versions of the CRTC_V_TOTAL and CRTC_V_DISP registers for use during DFP operations, These contain separate values used for panel output. They are used when FP_USE_SHADOW_EN field in FP_GEN_CNTL register is set to ‘1’.

FP_GEN_CNTL   MMR:0x0284 MMR_1:0x0284 IND:0x0284 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_ON 	0 	0x0 	This bit must be set to '1', along with other signals, to enable Digital Flat Panel (DFP) output. Enabling the TMDS transmitter for DFP output requires 1) a DFP-enabled chip, 2) the FP_ON bit must be '1', 3) the TMDS_EN field must be '1', and 4) the DIGON field (in the FP_PANEL_CNTL register) must be enabled. The TMDS_TRANSMITTER_CNTL register must also be set for TMDS output to be activated

 0=FP OFF 
 1=FP ON 

FP_BLANK_EN 	1 	0x1 	Setting this bit to 1 while the DFP interface is active will set the entire panel to blank black display (output consists of zeroes).

 0=Disable 
 1=Enable 

TMDS_EN 	2 	0x0 	This bit must be set to ‘1’, along with other bits, to enable Digital Flat Panel (DFP) output.
See FP_ON description for necessary registers.
The value of this register, TMDS_EN, will be reset to ‘0’ if Flat Panel detection is enabled and the detection circuitry detects a hot-plugable panel being disconnected from the graphics card. The DIGONregister bit (in FP_PANEL_CNTL) is also similarly reset.

 0=Disable 
 1=Enable 

PANEL_FORMAT 	3 	0x1 	Specifies the pixel format of the DFP being connected to the card
0 = 18 bits per pixel (666 RGB) TFT Panel 
1 = 24 bits per pixel (888 RGB) TFT Panel

 0=18 bit per pixel TFT panel - 666 RGB 
 1=24 bit per pixel TFT panel - 888 RGB 

NO_OF_GREY 	5:4 	0x0 	For an 18bpp panel specifies whether frame modulation is enabled, and if so, the number of grey levels per color component supported. Frame modulation provides the illusion that an 18bpp panel has as many color components as a 24bpp panel.  Only applies to 18bpp panels.
0 = no frame modulation
1 = 2 levels of grey per color component
2 = 4 levels of grey per color component

 0=No frame modulation 
 1=2 levels of grey support 
 2=4 levels of grey support 
 3=reserved 

FP_RST_FM 	6 	0x0 	0 = Enable Frame Modulation circuitry
1 = Reset Frame Modulation circuitry

 0=EnaFMCir 
 1=ResetFMCir 

FP_EN_TMDS (R) 	7 	0x0 	A read-only status bit that tells if the internal TMDS transmitted has been turned on. There are four conditions that need to be satisfied for this bit to be a ‘1’. 1) a DFP-enabled graphics chip, 2) the FP_ON bit must be ‘1’,3) the TMDS_EN field must be ‘1’, and 4) the DIGON field (in the FP_PANEL_CNTL register) must be enabled.

FP_DETECT_SENSE (R) 	8 	0x0 	A read only status bit that is set to '1' if a panel that supports hot-plugging is detected to be connected to the 
MONDET pin on the graphics chip
1 = panel connected
0 = no panel connected

	
FP_DETECT_INT_POL 	9 	0x0 	Sets the edge transition on the MONDET pin that will cause an interrupt, if enabled, to occur.
When a Flat Panel detection interrupt has occurred, this bit must be inverted in the same register write when clearing the FP_DETECT_INT_AK register.
1 = interrupt on the rising edge of MONDET
0 = interrupt on the falling edge of MONDET

FP_DETECT_INT_EN 	10 	0x0 	Enables interrupt generation when the edge event specified by FP_DETECT_INT_POL occurs.
1 = generate PCI interrupt when edge specified in FP_DETECT_INT_POL occurs on the MONDET pin
0 = no interrupts generated based on MONDET pin

FP_DETECT_INT_AK (W) 	11 	0x0 	Flat panel detection Interrupt Acknowledgement bit. This is a write-only bit. Need to invert FP_DETECT_INT_POL bit when writing this bit to clear the FP_DETECT interrupt.

When writing:
1 = clear the interrupt so the value read from this register bit is ‘0’.
0 = no action

FP_DETECT_INT (R) 	11 	0x0 	Status of Interrupt Even detection on Flat Panel MONDET pin (panel without hot plugging support is connected or no panel is connected) is LOW

This is a read-only bit.
When Reading:
1 = even specified in FP_DETECT_INT_POL has occurred on the MONDET pin
0 = specified event has not occurred on MONDET pin
	
FP_DETECT_EN 	12 	0x0 	Enable Flat Panel Monitor Detection circuitry to turn on TMDS Transmitter
1 = TMDS transmitter is disabled when MONDET pin (panel without hot plugging support is connected or no panel is connected) is LOW.
0 = Enabling of TMDS transmitter is independent of the state of the MONDET pin
This register is now disabled and has no effect on turning on the TMDS transmitter.

(reserved) 	15:13 	  	  
	
CRTC_DONT_SHADOW_VPAR 	16 	0x0 	1 = use non-shadowed (normal) values for the Vertical CRT parameters (Vertical Blank Start/End, Vertical Retrace(Sync) Start/End, Vertical Total)
0 = use shadowed values for the Vertical CRT parameters.

 0=Use Shadowed 
 1=Use non-shadowed 

CRTC_DONT_SHADOW_HEND 	17 	0x0 	1 = use non-shadowed (normal) value for Horizontal Display End
0 = use shadowed value for Horizontal Display End

 0=Use Shadowed HorzDispEnd 
 1=Use non-shadowed HorzDispEnd 

CRTC_USE_SHADOWED_VEND 	18 	0x0 	1 = use the shadowed version of the Vertical End Register
0 = use the non-shadowed (normal) version of the Vertical End Register

 0=disable 
 1=use shadowed VEND 

CRTC_USE_SHADOWED_ROWCUR 	19 	0x0 	1 = use the shadowed version of VGA Cursor Start (CRT0A_S (bits 4 to 0)), VGA Cursor End (CRT0B_S (4:0)), Max_Row_Scan (CRT09_S (4:0)), and Underline (CRT14_S (4:0)) Register.
0 = use the non-shadowed (normal version) of VGA Cursor Start, VGA Cursor End, Max_Row_Scan, and Underline.

 0=disable 
 1=use shadowed RowCur 

CRTC_HORZ_DIVBY2_EN 	20 	0x0 	1 = divide Horizontal CRT parameters by 2 when shadow registers are used and SEQ_PCLKBY2(in SEQ01 register) is active
0 = do not divide Horizontal CRT parameters by 2 when shadow registers are used and SEQ_PCLKBY2 is active.

 0=Disable 
 1=Enable 

CRTC_DIS_HOR_CRT_DIV_BY_2 	21 	0x0 	1 = use the divided version of the shadowed Horizontal Sync for the CRT
0 = use the non-shadowed (normal) version of the Horizontal Sync if CRTC_DIVBY2_EN=1

 0=Divide if HorzDivB2En = 1 
 1=Do not Divide 

CRTC_LOCK_8DOT 	22 	0x0 	1 = Character clock is forced to 8-dots per character
0 = Character clock can be 9-dot or 8-dot based on value in SEQ01 register

 0=9OR8dot 
 1=8dot 

CRT_SYNC_SEL 	23 	0x0 	Determine which CRT values should be used in centering mode for CRT
1 = use shadowed (LCD) values for CRT syncs (Horizontal and Vertical) in centering mode
0 = user non-shadowed (normal) values for CRT syncs in centering mode

 0=Use non-shadow values for CRT syncs in centering mode 
 1=Use shadow(LCD) values for CRT syncs in centering mode 

FP_USE_SHADOW_EN 	24 	0x0 	Enable the use of Shadow Registers
1 = Use the Shadow Registers to generate the DFP timing (except shadows CRT09_S(4;0), CRT14_S, CRT0A_S, CRT0B_S, and FP_CRTC_V_TOTAL_DISP(26:16))
0 = Uses the normal CRTC registers to generate the DFP timing.

 0=Disable 
 1=Enable 

DONT_RST_CHAREN 	25 	0x0 	When switching modes, the CHAREN I usually reset. This may not be good for flat panels. This bit should be set to ‘1’ when panel is in operation.
1 = Prevent value of SEQ00 from stopping the CHAREN signal
0 = Let SEQ00 stop the Character Enable signal

 0=Let SEQ00 stop CHAREN 
 1= Don't let SEQ00 stop CHAREN 

(reserved) 	31:26 	  	  
	
 FP_GEN_CNTL:  <No Description> 

FP_PANEL_CNTL   MMR:0x0288 MMR_1:0x0288 IND:0x0288 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
DIGON 	0 	0x0 	Flat Panel Digital Power Control
1 = Turn on Panel Digital Voltage
0 = Shut off panel Digital Voltage. The value of this register, DIGON, will be reset to ‘0’ if Flat Panel detection is enabled and the panel hot-plugging detection circuitry detects a panel being disconnected from the graphics card. The TMDS_EN register bit is also similarly reset. This bit must be enabled, in addition to FP_ON, TMDS_EN, and FP_PANEL_DETECT (if hot plugging is enabled via the FP_DETECT_ENABLE bit in FP_GEN_CNTL) for the internal TMDS transmitter to be enabled.

 0=Panel Digital Voltage off 
 1=Panel Digital Voltage On 

BLON 	1 	0x0 	Flat Panel Backlight Control
 1 = Turn on Panel Backlight Voltage (Vb)
 0 = Shut off Panel Backlight Voltage

BLMOD_EN 	2 	0x0 	Enables Backlight Modulation on Flat Panel
1 = Backlight (brightness) modulation enabled
0 = Backlight modulation disabled. When BLON is enabled and BLMOD_EN is set to 0 the Backlight will be set to full intensity.

BL_CLK_SEL 	3 	0x0 	Clock select for Backlight Modulation
(Note: Clock Crystal frequency may be 29 MHz or 14.5 MHz)

1 = crystal frequency (ie.e 29 MHz) divided by 3
0 = crystal frequency

 0=29MHz Backlight Modulation Clock 
 1=29MHz divided by 3 Backlight Modulation Clock 

BLON_DIGON_OUT_EN 	4 	0x0 	Enables output of BLON (panel backlight) and DIGON (panel digital power) signals on the MONID0 and MONID3 pins, respectively, since these pins are shared with other functionality.

1 = BLON and DIGON output on MONID0/MONID3 is enabled
0 = output of BLON and DIGON disabled.

 0=BLON and DIGON pins are used for other functionality 
 1=BLON and DIGON pins (MONID0/3) are enabled 

FP_DTMG_POL 	5 	0x0 	Sets the Polarity for the Flat Panel Display Enable signal
1 = Negative polarity (active low)
0 = Positive polarity (active high)

 0=active high Display Enable 
 1=active low Display Enable 

(reserved) 	7:6 	  	  
	
BL_MOD_LEVEL 	15:8 	0x0 	Setting for Backlight Modulation intensity. This value is utilized when BLMOD_EN is set to ‘1’.

0 = backlight is set to the dimmest setting
255 = backlight is always on (brightest setting)

(reserved) 	31:16 	  	  
	
 FP_PANEL_CNTL:  Digital Flat Panel Interface Control Registers

FP_HORZ_STRETCH   MMR:0x028C MMR_1:0x028C IND:0x028C 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_HORZ_STRETCH_RATIO 	15:0 	0x0 	Horizontal Stretch Ratio for Ratiometric Expansion.
When FP_HORZ_STRETCH_MODE=0 (stretching), the value in this register is shifted out serially (LSB first, i.e. bit 0).  If the bit shifted out is a 1, the previous pixel is duplicated and displayed.  If the bit shifted out is a 0, the next real display pixel is displayed.  The bit shifter is loops back to bit 0 from either bit 9, 11, 12, 14, or 15 depending on the value of FP_LOOP_STRETCH.  In stretching mode, bit '0' of the ratio must be set to 0.
When FP_HORZ_STRETCH_MODE=1 (blending), only the 12 LSB (bits 11 to 0) are used and the ratio should be set to:
FP_HORZ_STRETCH_RATIO = [ source_width / destination_width ] * 4096

	
FP_HORZ_PANEL_SIZE 	23:16 	0x0 	Specifies the horizontal size of the Flat Panel in characters ( pixels/8 - 1 )
This value is used when in VGA mode and FP_AUTO_HORZ_RATIO = '1' to automatically ratiometrically expand any VGA resolution to fill the Flat Panel display horizontally.

	
FP_AUTO_HORZ_RATIO 	24 	0x0 	Enables automatic horizontal stretch ratio calculation (in VGA modes only) based on actual VGA horizontal display and VGA overscan values instead of using the H_DISP_END, OVR_WID_LEFT, and OVR_WID_RIGHT register values.
1 = Enable Auto Horizontal Stretch Ratio calculation
0 = Disable Auto Horizontal Stretch Ratio

FP_HORZ_STRETCH_MODE 	25 	0x0 	Specifies stretching method used for horizontal ratiometric expansion
1 = Horizontal blending 
0 = Pixel Replication (Stretching) (pattern based on FP_HORZ_STRETCH_RATIO shift register field)

 0=pixel replication 
 1=horizontal blending 

FP_HORZ_STRETCH_EN 	26 	0x0 	Enables the Horizontal Stretching circuitry
1 = Horizontal Stretching Enabled
0 = Horizontal Stretching Disabled

 0=disable 
 1=enable 

FP_LOOP_STRETCH 	29:27 	0x0 	Specifies the bit at which the FP_HORZ_STRETCH_RATIO shift register loops back to bit 0 when Pixel Replication and Horizontal Stretching are Enabled.
000 = Loop bit 0 back to bit 9
001 = Loop bit 0 back to bit 11
010 = Loop bit 0 back to bit 12
011 = Loop bit 0 back to bit 14
100 = Loop bit 0 back to bit 15
others = reserved

 0=loop bit 0 back to bit 9 
 1=loop bit 0 back to bit 11 
 2=loop bit 0 back to bit 12 
 3=loop bit 0 back to bit 14 
 4=loop bit 0 back to bit 15 

(reserved) 	30 	  	  
	
FP_AUTO_HORZ_RATIO_FIX_EN 	31 	0x1 	Enables a fix for Automation Horizontal Ratio Generation in VGA modes with non-standard register values.
1 = auto horizontal ratio generation with fix for non-standard VGA settings 
 0 = normal auto horizontal ratio generation in VGA modes 

 FP_HORZ_STRETCH:  Flat Panel and CRT Horizontal Ratiometric Expansion Control Registers 

FP_VERT_STRETCH   MMR:0x0290 MMR_1:0x0290 IND:0x0290 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_VERT_PANEL_SIZE 	10:0 	0x0 	Specifies the vertical size of the Flat Panel (vertical lines - 1).
This value is used when in VGA mode and FP_AUTO_HORZ_RATIO = '1' to automatically ratiometrically expand any VGA display mode's resolution to fill the Flat Panel display vertically.

FP_VERT_STRETCH_RATIO 	20:11 	0x0 	Vertical Stretch Ratio for Ratiometric Expansion. Applies to both Vertical Blending and Line Replication.
FP_VERT_STRETCH_RATIO = [ no of lines of source / no of lines of destination ] * 1024

(reserved) 	23:21 	  	  
	
FP_VERT_STRETCH_EN 	24 	0x0 	Enable Vertical Stretching Ratiometric Expansion circuitry
1 = Vertical Stretching enabled
0 = Vertical Stretching disabled

FP_VERT_STRETCH_MODE 	25 	0x0 	Vertical Stretching mode
1 = vertical line blending
0 = line replication

 0=line replication 
 1=vertical blending 

FP_AUTO_VERT_RATIO 	26 	0x0 	Enables automatic calculation of the vertical ratio in VGA modes based on the VGA values for vertical display end, top overscan, and bottom overscan.
1 = enable automatic calculation of vertical ratio for VGA modes
0 = use value of FP_VERT_STRETCH_RATIO register as vertical ratio

 0=use VERT_STRETCH_RATIOX 
 1=calculate vertical ratio 

VERT_LNBUF_EXTSENSE 	27 	0x1 	Vertical Line Buffer Macro Extended Sense enable bit
1 = Extended Sense enabled (default value)
0 = Extended Sense disabled

(reserved) 	31:28 	  	  
	
 FP_VERT_STRETCH:  Flat Panel and CRT Vertical Ratiometric Expansion Control Registers 

TMDS_CRC   MMR:0x02A0 MMR_1:0x02A0 IND:0x02A0 
  [R]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
TMDS_CRCRGB 	29:0 	0x0 	30-bit CRC based on the TMDS encoder output data.
(Read-only register).

(reserved) 	31:30 	  	  
	
 TMDS_CRC:  TMDS Cyclic Redundancy Check output register. In TMDS_CNTL, the TMDS_CRC_EN field enables the CRC generator.

FP_H_SYNC_STRT_WID   MMR:0x02C4 MMR_1:0x02C4 IND:0x02C4 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_H_SYNC_STRT_PIX 	2:0 	0x0 	Shadow version of Horizontal Sync start delay (in pixels). Allows pixel accurate horizontal positioning by delaying the sync position within the character specified by the FP_H_SYNC_STRT_CHAR register.

FP_H_SYNC_STRT_CHAR 	11:3 	0x0 	Shadow version of the Horizontal Sync start (pixels * 8). Sum of the display width, overscan right and front porch.

(reserved) 	15:12 	  	  
	
FP_H_SYNC_WID 	21:16 	0x0 	Shadow version of the Horizontal  Sync width (pixels * 8)

(reserved) 	22 	  	  
	
FP_H_SYNC_POL 	23 	0x0 	Shadow version of the Horizontal Sync polarity
1 = Negative Polarity (active low)
0 =Positive Polarity (active high)

FP_H_SYNC_PIX_DELAY 	27:24 	0x0 	Panel Horizontal Sync additional delay. Enables extra delay (in units of pixel clocks) to be added to the Horizontal Sync signal going to the Panel. Range is from 0 to 15 pixel clocks additional delay. Default is 0.

(reserved) 	31:28 	  	  
	
 FP_H_SYNC_STRT_WID : Shadow versions of the CRTC Horizontal Sync related registers. These contain separate values for panel output and are used when the FP_USE_SHADOW_EN field in FP_GEN_CNTL register is set to ‘1’.

FP_V_SYNC_STRT_WID   MMR:0x02C8 MMR_1:0x02C8 IND:0x02C8 
 [RW]  32 bits   (access:  8/16/32) 	
Field Name	Bits	Default	Description	
FP_V_SYNC_STRT 	10:0 	0x0 	Shadow version of the Vertical Sync start. Sun of display height, overscan bottom and front porch.

(reserved) 	15:11 	  	  
	
FP_V_SYNC_WID 	20:16 	0x0 	Shadow version of Vertical Sync width.
	
(reserved) 	22:21 	  	  
	
FP_V_SYNC_POL 	23 	0x0 	Shadow version of the Vertical Sync polarity

1 = Negative Polarity (active low)
0 =Positive Polarity (active high) 

(reserved) 	31:24 	  	  
	
 FP_V_SYNC_STRT_WID: Shadow versions of the CRTC Vertical Sync related registers. These contain separate values for panel output and are used when the FP_USE_SHADOW_EN field in FP_GEN_CNTL register is set to ‘1’.